UVM / FPGA Verification Engineer
FPGA Verification Engineer
Join a team of World-Class engineers and work on today's most cutting edge products in a variety of settings. Great Team and compensation!
About the Opportunity
Duties and Responsibilities
The FPGA Verification Specialist will work in an exciting team environment and will have the following responsibilities:
- Priming the verification activities for a block or an entire chip.
- Architecting the verification environment using OVM and writing the associated documentation.
- Participating in the test case writing activity.
- Using constrained random verification approaches when possible.
- Using direct test cases to support lab bring-up.
- Performing code coverage and functional coverage
A minimum of 5 years of relevant experience in FPGA Verification.
Familiarity with System Verilog, OVM/UVM, Verilog (mainly), VHDL, and scripting languages.
Familiarity with SONET, OTN, Ethernet, PCIe.
Familiarity with constrained verification techniques, assertions and functional coverage.
Excellent communication skills.
Our client is located in Ottawa’s West end (Kanata). For further details and consideration, qualified candidates are invited to apply online or send their resume directly to firstname.lastname@example.org